Re: [PATCH] PCI/DPC: Quirk PIO log size for certain Intel PCIe root ports

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[Adding Sasha for visibility]

Hi Mika,

> There is a BIOS bug on Intel Tiger Lake and Alder Lake systems that
> accidentally clears the root port PIO log size even though it should be 4.
> Fix the affected root ports by forcing the log size to be 4 if it is set
> to 0. The BIOS for the next generation CPUs should have this fixed.

Thank you for the fix!

> Link: https://bugzilla.kernel.org/show_bug.cgi?id=209943

I've added Sasha, as there is probably a lot of the 11th and 12th
generation of Intel hardware out there that might warrant a backport
to stable kernels.

	Krzysztof



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