On 22/06/2022 23:58, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > Hardware random, PCI and clock drivers for the PolarFire SoC have been > upstreamed but are not covered by the MAINTAINERS entry, so add them. > Daire is the author of the clock & PCI drivers, so add him as a > maintainer in place of Lewis. > > Acked-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx> > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Arnd, Palmer: Does the SoC tree make more sense for this patch? I am missing an ack from Herbert (but I don't think that's blocking for a MAINTAINERS update to my own entry?). If SoC is the better option, should I resend this to soc@xxxxxxxxxx? Unfortunately, since I originally sent this patch there have been other changes to this entry that will conflict in -next (all are additions so easily resolved...). I was hoping to get this patch applied to v5.19-rc(foo) since we never added maintainers entries for these drivers rather than wait for v5.20. If you (plural) would rather wait for v5.20, I can resubmit this patch after v5.20-mw1 with an additional i2c entry (if the driver is applied) that already has an ack from Wolfram. Thanks, Conor. > --- > MAINTAINERS | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index a6d3bd9d2a8d..01a7bfa49bdc 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -17136,12 +17136,15 @@ N: riscv > K: riscv > > RISC-V/MICROCHIP POLARFIRE SOC SUPPORT > -M: Lewis Hanly <lewis.hanly@xxxxxxxxxxxxx> > M: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > +M: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> > L: linux-riscv@xxxxxxxxxxxxxxxxxxx > S: Supported > F: arch/riscv/boot/dts/microchip/ > +F: drivers/char/hw_random/mpfs-rng.c > +F: drivers/clk/microchip/clk-mpfs.c > F: drivers/mailbox/mailbox-mpfs.c > +F: drivers/pci/controller/pcie-microchip-host.c > F: drivers/soc/microchip/ > F: include/soc/microchip/mpfs.h >
