From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Hardware random, PCI and clock drivers for the PolarFire SoC have been upstreamed but are not covered by the MAINTAINERS entry, so add them. Daire is the author of the clock & PCI drivers, so add him as a maintainer in place of Lewis. Acked-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> --- MAINTAINERS | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index a6d3bd9d2a8d..01a7bfa49bdc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17136,12 +17136,15 @@ N: riscv K: riscv RISC-V/MICROCHIP POLARFIRE SOC SUPPORT -M: Lewis Hanly <lewis.hanly@xxxxxxxxxxxxx> M: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> +M: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> L: linux-riscv@xxxxxxxxxxxxxxxxxxx S: Supported F: arch/riscv/boot/dts/microchip/ +F: drivers/char/hw_random/mpfs-rng.c +F: drivers/clk/microchip/clk-mpfs.c F: drivers/mailbox/mailbox-mpfs.c +F: drivers/pci/controller/pcie-microchip-host.c F: drivers/soc/microchip/ F: include/soc/microchip/mpfs.h -- 2.36.1
