On Fri, Jun 24, 2022 at 05:34:21PM +0300, Serge Semin wrote:
> There are several places in the common DW PCIe code with incoherent local
> variables usage: a variable is defined and initialized with a structure
> field, but the structure pointer is de-referenced to access that field
> anyway; the local variable is defined and initialized but either used just
> once or not used afterwards in the main part of the subsequent method.
> It's mainly concerns the pcie_port.dev field. Let's fix that in the
> relevant places.
>
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Thanks,
Mani
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
>
> ---
>
> Changelog v4:
> - This is a new patch created on the v4 lap of the series.
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 12 ++++++------
> drivers/pci/controller/dwc/pcie-designware.c | 8 +++-----
> 2 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 9a4922b714e5..54257874c154 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -296,7 +296,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
> struct resource *cfg_res;
> int ret;
>
> - raw_spin_lock_init(&pci->pp.lock);
> + raw_spin_lock_init(&pp->lock);
>
> cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> if (cfg_res) {
> @@ -388,15 +388,15 @@ int dw_pcie_host_init(struct pcie_port *pp)
> dw_chained_msi_isr,
> pp);
>
> - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
> + ret = dma_set_mask(dev, DMA_BIT_MASK(32));
> if (ret)
> - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
> + dev_warn(dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
>
> - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
> + pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg,
> sizeof(pp->msi_msg),
> DMA_FROM_DEVICE,
> DMA_ATTR_SKIP_CPU_SYNC);
> - ret = dma_mapping_error(pci->dev, pp->msi_data);
> + ret = dma_mapping_error(dev, pp->msi_data);
> if (ret) {
> dev_err(pci->dev, "Failed to map MSI data\n");
> pp->msi_data = 0;
> @@ -633,7 +633,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> }
>
> if (pci->num_ob_windows <= atu_idx)
> - dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)\n",
> + dev_warn(dev, "Resources exceed number of ATU entries (%d)\n",
> pci->num_ob_windows);
> }
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index f9613835212b..ce01187947c9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -677,8 +677,7 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
>
> void dw_pcie_iatu_detect(struct dw_pcie *pci)
> {
> - struct device *dev = pci->dev;
> - struct platform_device *pdev = to_platform_device(dev);
> + struct platform_device *pdev = to_platform_device(pci->dev);
>
> pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
> if (pci->iatu_unroll_enabled) {
> @@ -687,7 +686,7 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
> platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
> if (res) {
> pci->atu_size = resource_size(res);
> - pci->atu_base = devm_ioremap_resource(dev, res);
> + pci->atu_base = devm_ioremap_resource(pci->dev, res);
> }
> if (!pci->atu_base || IS_ERR(pci->atu_base))
> pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
> @@ -711,9 +710,8 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
>
> void dw_pcie_setup(struct dw_pcie *pci)
> {
> + struct device_node *np = pci->dev->of_node;
> u32 val;
> - struct device *dev = pci->dev;
> - struct device_node *np = dev->of_node;
>
> if (pci->link_gen > 0)
> dw_pcie_link_set_max_speed(pci, pci->link_gen);
> --
> 2.35.1
>
--
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