On Fri, Jun 24, 2022 at 05:34:16PM +0300, Serge Semin wrote: > Currently the embedded CDM IOs consistency check-engine is enabled only if > the num_lanes field of dw_pcie structure is set to non-zero value. It's > definitely wrong since the CDM checking has nothing to do with the PCIe > lanes settings, while that feature will be left disabled for the platforms > which expect it being enabled and prefer keeping the default lanes setup. > Let's fix that by enabling the CDM-check feature before the num_lanes > parameter is handled. > > Fixes: 07f123def73e ("PCI: dwc: Add support to enable CDM register check") Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Thanks, Mani > Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx> > Reviewed-by: Vidya Sagar <vidyas@xxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > --- > > Changelog v4: > - This is a new patch created on v4 lap of the series. > --- > drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 347251bf87d0..5848cc520b52 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -740,6 +740,13 @@ void dw_pcie_setup(struct dw_pcie *pci) > val |= PORT_LINK_DLL_LINK_EN; > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); > > + if (of_property_read_bool(np, "snps,enable-cdm-check")) { > + val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); > + val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | > + PCIE_PL_CHK_REG_CHK_REG_START; > + dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); > + } > + > of_property_read_u32(np, "num-lanes", &pci->num_lanes); > if (!pci->num_lanes) { > dev_dbg(pci->dev, "Using h/w default number of lanes\n"); > @@ -786,11 +793,4 @@ void dw_pcie_setup(struct dw_pcie *pci) > break; > } > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); > - > - if (of_property_read_bool(np, "snps,enable-cdm-check")) { > - val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); > - val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | > - PCIE_PL_CHK_REG_CHK_REG_START; > - dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); > - } > } > -- > 2.35.1 > -- மணிவண்ணன் சதாசிவம்