On Thu, Jun 16, 2022 at 06:14:27PM +0530, Bharat Kumar Gogada wrote: > Xilinx Versal Premium series has CPM5 block which supports Root Port > functioning at Gen5 speed. > > Xilinx Versal CPM5 has few changes with existing CPM block. > - CPM5 has dedicated register space for control and status registers. > - CPM5 legacy interrupt handling needs additonal register bit > to enable and handle legacy interrupts. > > Changes in v5: > - Added of_device_get_match_data to identify CPM version. > > > Bharat Kumar Gogada (2): > dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port > PCI: xilinx-cpm: Add support for Versal CPM5 Root Port > > .../bindings/pci/xilinx-versal-cpm.yaml | 48 ++++++++++++-- > drivers/pci/controller/pcie-xilinx-cpm.c | 62 ++++++++++++++++++- > 2 files changed, 103 insertions(+), 7 deletions(-) Weren't you going to include a MAINTAINERS update here? https://lore.kernel.org/r/BY5PR02MB6947C5B34801AD5F289127ABA5A69@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Maybe I missed it? Thanks, Bjorn
