On Mon, Jun 13, 2022 at 11:16:41PM +0300, Andy Shevchenko wrote:
> The resource management improve for PCI on x86 broke booting of Intel MID
> platforms. It seems that the current code removes all available resources
> from the list and none of the PCI device may be initialized. Restore the
> old behaviour by force disabling the e820 usage for the resource allocation.
>
> Fixes: 4c5e242d3e93 ("x86/PCI: Clip only host bridge windows for E820 regions")
> Depends-on: fa6dae5d8208 ("x86/PCI: Add kernel cmdline options to use/ignore E820 reserved regions")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Yeah, I blew it with 4c5e242d3e93. Can you provide more details on
how the MID platforms broke? Since you set "pci_use_e820 = false" for
MID below, I assume MID doesn't depend on the e820 clipping and thus
should not break if we turn off clipping by default in 2023 as in
0ae084d5a674 ("x86/PCI: Disable E820 reserved region clipping starting
in 2023"). But it'd be nice to see the dmesg log and make sure.
> ---
> arch/x86/include/asm/pci_x86.h | 1 +
> arch/x86/pci/acpi.c | 2 +-
> arch/x86/pci/intel_mid_pci.c | 1 +
> 3 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
> index f52a886d35cf..503f83fbc686 100644
> --- a/arch/x86/include/asm/pci_x86.h
> +++ b/arch/x86/include/asm/pci_x86.h
> @@ -126,6 +126,7 @@ extern const struct pci_raw_ops *raw_pci_ext_ops;
> extern const struct pci_raw_ops pci_mmcfg;
> extern const struct pci_raw_ops pci_direct_conf1;
> extern bool port_cf9_safe;
> +extern bool pci_use_e820;
>
> /* arch_initcall level */
> #ifdef CONFIG_PCI_DIRECT
> diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
> index a4f43054bc79..ac2f220d50fc 100644
> --- a/arch/x86/pci/acpi.c
> +++ b/arch/x86/pci/acpi.c
> @@ -20,7 +20,7 @@ struct pci_root_info {
> #endif
> };
>
> -static bool pci_use_e820 = true;
> +bool pci_use_e820 = true;
> static bool pci_use_crs = true;
> static bool pci_ignore_seg;
>
> diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
> index 8edd62206604..7869b86bff04 100644
> --- a/arch/x86/pci/intel_mid_pci.c
> +++ b/arch/x86/pci/intel_mid_pci.c
> @@ -313,6 +313,7 @@ int __init intel_mid_pci_init(void)
> pcibios_enable_irq = intel_mid_pci_irq_enable;
> pcibios_disable_irq = intel_mid_pci_irq_disable;
> pci_root_ops = intel_mid_pci_ops;
> + pci_use_e820 = false;
> pci_soc_mode = 1;
> /* Continue with standard init */
> acpi_noirq_set();
> --
> 2.35.1
>
