Hi Rob, On Thu, 14 Apr 2022 13:15:30 -0500 Rob Herring <robh@xxxxxxxxxx> wrote: > On Thu, Apr 14, 2022 at 09:40:05AM +0200, Herve Codina wrote: > > Convert Renesas PCI bridge bindings documentation to json-schema. > > Also name it 'renesas,pci-usb' as it is specifically used to > > connect the PCI USB controllers to AHB bus. > > Please name it based on compatible strings. renesas,pci-rcar-gen2.yaml Ok, renamed. > > > > > Signed-off-by: Herve Codina <herve.codina@xxxxxxxxxxx> > > --- > > .../devicetree/bindings/pci/pci-rcar-gen2.txt | 84 ----------- > > .../bindings/pci/renesas,pci-usb.yaml | 134 ++++++++++++++++++ > > 2 files changed, 134 insertions(+), 84 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt > > create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-usb.yaml > > > > diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt > > deleted file mode 100644 ... > > diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-usb.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-usb.yaml > > new file mode 100644 ... > > index 000000000000..3f8d79b746c7 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/renesas,pci-usb.yaml > > @@ -0,0 +1,134 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/renesas,pci-usb.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas AHB to PCI bridge > > + > > +maintainers: > > + - Marek Vasut <marek.vasut+renesas@xxxxxxxxx> > > + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> > > + > > +description: | > > + This is the bridge used internally to connect the USB controllers to the > > + AHB. There is one bridge instance per USB port connected to the internal > > + OHCI and EHCI controllers. > > + > > +allOf: > > + - $ref: /schemas/pci/pci-bus.yaml# > > + > > +properties: > > + compatible: > > + oneOf: > > + - items: > > + - enum: > > + - renesas,pci-r8a7742 # RZ/G1H > > + - renesas,pci-r8a7743 # RZ/G1M > > + - renesas,pci-r8a7744 # RZ/G1N > > + - renesas,pci-r8a7745 # RZ/G1E > > + - renesas,pci-r8a7790 # R-Car H2 > > + - renesas,pci-r8a7791 # R-Car M2-W > > + - renesas,pci-r8a7793 # R-Car M2-N > > + - renesas,pci-r8a7794 # R-Car E2 > > + - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1 > > + > > + reg: > > + description: | > > + A list of physical regions to access the device. The first is > > + the operational registers for the OHCI/EHCI controllers and the > > + second is for the bridge configuration and control registers. > > + minItems: 2 > > + maxItems: 2 > > + > > + interrupts: > > + description: Interrupt for the device. > > + > > + interrupt-map: > > + description: | > > + Standard property used to define the mapping of the PCI interrupts > > + to the GIC interrupts. > > + > > + interrupt-map-mask: > > + description: > > + Standard property that helps to define the interrupt mapping. > > + > > + clocks: > > + description: The reference to the device clock. > > + > > + bus-range: > > + description: | > > + The PCI bus number range; as this is a single bus, the range > > + should be specified as the same value twice. > > items: > const: 0 Well, some other values are present in some dtsi files such as 'bus_range = <1 1>;' or 'bus_range = <2 2>;' in r8a7742.dtsi. The constraint is to have the same value twice. Is there a way to specify this constraint ? > > > + > > + "#address-cells": > > + const: 3 > > + > > + "#size-cells": > > + const: 2 > > + > > + "#interrupt-cells": > > + const: 1 > > All these are defined by pci-bus.yaml Right. Replaced by: "#address-cells": true "#size-cells": true "#interrupt-cells": true Is that correct ? > > > + > > + dma-ranges: > > + description: | > > + A single range for the inbound memory region. If not supplied, > > + defaults to 1GiB at 0x40000000. Note there are hardware restrictions on > > + the allowed combinations of address and size. > > 'a single range' == 'maxItems: 1' Ok, maxItems added. > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - interrupt-map > > + - interrupt-map-mask > > + - clocks > > + - bus-range > > + - "#address-cells" > > + - "#size-cells" > > + - "#interrupt-cells" > > + > > +unevaluatedProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/r8a7790-cpg-mssr.h> > > + > > + bus { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + pci0: pci@ee090000 { > > + compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; > > + device_type = "pci"; > > + clocks = <&cpg CPG_MOD 703>; > > + reg = <0 0xee090000 0 0xc00>, > > + <0 0xee080000 0 0x1100>; > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > Don't disable your example. Ok, done Thanks for the review. Hervé -- Hervé Codina, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
