On Fri, 14 Oct 2011 14:56:13 -0500 Jon Mason <mason@xxxxxxxx> wrote: > Intel 5000 and 5100 series memory controllers have a known issue if read > completion coalescing is enabled and the PCI-E Maximum Payload Size is > set to 256B. To work around this issue, disable read completion > coalescing in the memory controller and root complexes. Unfortunately, > it must always be disabled, even if no 256B MPS devices are present, due > to the possibility of one being hotplugged. > > Links to erratas: > http://www.intel.com/content/dam/doc/specification-update/5000-chipset-memory-controller-hub-specification-update.pdf > http://www.intel.com/content/dam/doc/specification-update/5100-memory-controller-hub-chipset-specification-update.pdf > > Thanks to Jesse Brandeburg and Ben Hutchings for providing insight into > the problem. Applied this series to -next, thanks Jon. -- Jesse Barnes, Intel Open Source Technology Center
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