On Tue, 30 Aug 2011 10:56:16 -0600 Myron Stowe <myron.stowe@xxxxxxxxxx> wrote: > From: Myron Stowe <mstowe@xxxxxxxxxx> > > The 'latency timer' of PCI devices, both Type 0 and Type 1, > is setup in architecture-specific code [see: 'pcibios_set_master()']. > There are two approaches being taken by all the architectures - check > if the 'latency timer' is currently set between 16 and 255 and if not > bring it within bounds, or, do nothing (and then there is the > gratuitously different parisc implementation). > > There is nothing architecture-specific about PCI's 'latency timer' so > this patch pulls its setup functionality up into the PCI core by > creating a generic 'pcibios_set_master()' function using the 'weak' > attribute which can be used by all architectures as a default which, > if absolutely necessary, can then be over-ridden by architecture- > specific code. > > No functional change. Ok applied this series to -next, thanks. -- Jesse Barnes, Intel Open Source Technology Center
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