On Thu, Mar 24, 2022 at 04:25:15AM +0300, Serge Semin wrote:
> In accordance with the dw_pcie_setup_rc() method semantics and judging by
> what the comment added in commit dd193929d91e ("PCI: designware: Explain
> why we don't program ATU for some platforms") states there are DWC
> PCIe-available platforms like Keystone (pci-keystone.c) or Amazon's
> Annapurna Labs (pcie-al.c) which don't have the DW PCIe internal ATU
> enabled and use it's own address translation approach implemented. In
> these cases at the very least there is no point in touching the DW PCIe
> iATU CSRs. Moreover depending on the vendor-specific address translation
> implementation it might be even erroneous. So let's move the iATU windows
> disabling procedure to being under the corresponding conditional statement
> clause thus performing that procedure only if the iATU is expected to be
> available on the platform.
>
> Fixes: 458ad06c4cdd ("PCI: dwc: Ensure all outbound ATU windows are reset")
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Thanks,
Mani
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f89e6552139b..a048d88e0c30 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -566,7 +566,6 @@ static struct pci_ops dw_pcie_ops = {
>
> void dw_pcie_setup_rc(struct pcie_port *pp)
> {
> - int i;
> u32 val, ctrl, num_ctrls;
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>
> @@ -618,19 +617,22 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
> dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
>
> - /* Ensure all outbound windows are disabled so there are multiple matches */
> - for (i = 0; i < pci->num_ob_windows; i++)
> - dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
> -
> /*
> * If the platform provides its own child bus config accesses, it means
> * the platform uses its own address translation component rather than
> * ATU, so we should not program the ATU here.
> */
> if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> - int atu_idx = 0;
> + int i, atu_idx = 0;
> struct resource_entry *entry;
>
> + /*
> + * Ensure all outbound windows are disabled so there are
> + * multiple matches
> + */
> + for (i = 0; i < pci->num_ob_windows; i++)
> + dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
> +
> /* Get last memory resource entry */
> resource_list_for_each_entry(entry, &pp->bridge->windows) {
> if (resource_type(entry->res) != IORESOURCE_MEM)
> --
> 2.35.1
>
