On Tue, Dec 07, 2021 at 11:49:21AM +0100, Sergio Paracuellos wrote:
> PCI core code call 'pcibios_root_bridge_prepare()' function inside function
> 'pci_register_host_bridge()'. This point is very good way to properly enter
> into this MIPS ralink specific code to properly setup I/O coherency units
> with PCI memory addresses.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
FWIW:
Reviewed-by: Guenter Roeck <linux@xxxxxxxxxxxx>
> ---
> arch/mips/ralink/mt7621.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
> index bd71f5b14238..d6efffd4dd20 100644
> --- a/arch/mips/ralink/mt7621.c
> +++ b/arch/mips/ralink/mt7621.c
> @@ -10,6 +10,8 @@
> #include <linux/slab.h>
> #include <linux/sys_soc.h>
> #include <linux/memblock.h>
> +#include <linux/pci.h>
> +#include <linux/bug.h>
>
> #include <asm/bootinfo.h>
> #include <asm/mipsregs.h>
> @@ -22,6 +24,35 @@
>
> static void *detect_magic __initdata = detect_memory_region;
>
> +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
> +{
> + struct resource_entry *entry;
> + resource_size_t mask;
> +
> + entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
> + if (!entry) {
> + pr_err("Cannot get memory resource\n");
> + return -EINVAL;
> + }
> +
> + if (mips_cps_numiocu(0)) {
> + /*
> + * Hardware doesn't accept mask values with 1s after
> + * 0s (e.g. 0xffef), so warn if that's happen
> + */
> + mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
> + WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
> +
> + write_gcr_reg1_base(entry->res->start);
> + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
> + pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
> + (unsigned long long)read_gcr_reg1_base(),
> + (unsigned long long)read_gcr_reg1_mask());
> + }
> +
> + return 0;
> +}
> +
> phys_addr_t mips_cpc_default_phys_base(void)
> {
> panic("Cannot detect cpc address");
> --
> 2.33.0
>
