On Tue, Nov 23, 2021 at 11:33 PM Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> wrote: > > On Wed, Nov 24, 2021 at 08:28:24AM +0100, Christoph Hellwig wrote: > > On Tue, Nov 23, 2021 at 11:17:55PM -0800, Dan Williams wrote: > > > I am missing the counter proposal in both Bjorn's and your distaste > > > for aux bus and PCIe portdrv? > > > > Given that I've only brought in in the last mail I have no idea what > > the original proposal even is. > > Neither do I :( To be clear I am also trying to get to the root of Bjorn's concern. The proposal in $SUBJECT is to build on / treat a CXL topology as a Linux device topology on /sys/bus/cxl that references devices on /sys/bus/platform (CXL ACPI topology root and Host Bridges) and /sys/bus/pci (CXL Switches and Endpoints). This CXL port device topology has already been shipping for a few kernel cycles. What is on the table now is a driver for CXL port devices (a logical Linux construct). The driver handles discovery of "component registers" either by ACPI table or PCI DVSEC and offers services to proxision CXL regions. CXL 'regions' are also proposed as Linux devices that represent an active CXL memory range which can interleave multiple endpoints across multiple switches and host bridges.
