On Tue, Nov 23, 2021 at 10:33 PM Christoph Hellwig <hch@xxxxxx> wrote: > > On Tue, Nov 23, 2021 at 04:40:06PM -0800, Dan Williams wrote: > > Let me ask a clarifying question coming from the other direction that > > resulted in the creation of the auxiliary bus architecture. Some > > background. RDMA is a protocol that may run on top of Ethernet. > > No, RDMA is a concept. Linux supports 2 and a half RDMA protocols > that run over ethernet (RoCE v1 and v2 and iWarp). Yes, I was being too coarse, point taken. However, I don't think that changes the observation that multiple vendors are using aux bus to share a feature driver across multiple base Ethernet drivers. > > > Consider the case where you have multiple generations of Ethernet > > adapter devices, but they all support common RDMA functionality. You > > only have the one PCI device to attach a unique Ethernet driver. What > > is an idiomatic way to deploy a module that automatically loads and > > attaches to the exported common functionality across adapters that > > otherwise have a unique native driver for the hardware device? > > The whole aux bus drama is mostly because the intel design for these > is really fucked up. All the sane HCAs do not use this model. All > this attchment crap really should not be there. I am missing the counter proposal in both Bjorn's and your distaste for aux bus and PCIe portdrv? > > Another example, the Native PCIe Enclosure Management (NPEM) > > specification defines a handful of registers that can appear anywhere > > in the PCIe hierarchy. How can you write a common driver that is > > generically applicable to any given NPEM instance? > > Another totally messed up spec. But then pretty much everything coming > from the PCIe SIG in terms of interface tends to be really, really > broken lately. DVSEC and DOE is more of the same in terms of composing add-on features into devices. Hardware vendors want to mix multiple hard-IPs into a single device, aux bus is one response. Topology specific buses like /sys/bus/cxl are another. This CXL port driver is offering enumeration, link management, and memory decode setup services to the rest of the topology. I see it as similar to management protocol services offered by libsas.
