On Tue, Aug 23, 2011 at 6:13 PM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote: > Your error is "SP5100 TCO timer: mmio address 0xbafe00 already in > use". (Same error, but different address.) That looks like it's in > the middle of your RAM, i.e., it looks completely bogus. Given the > ugliness of the sp5100_tco driver, that doesn't surprise me. Possibly > the BIOS configured it differently and we tried to read the MMIO > address from the wrong (hard-coded) I/O ports. If we can dig up a > spec for this device, maybe this could be fixed up. I don't really have time to work on this, unfortunately, but here's a little info in case somebody else can. Specs: http://support.amd.com/us/Embedded_TechDocs/44413.pdf SP5100 Register Reference Guide http://support.amd.com/us/Embedded_TechDocs/44414.pdf SP5100 Register Programming Requirements http://support.amd.com/us/Embedded_TechDocs/44415.pdf SP5100 BIOS Developer's Guide I think the BDG has an example putting the watchdog at 0xfec000f0, which is where Ralf's system has it. The power-up default looks like 0, so if you have 0xbafe00, so either the BIOS put it somewhere nonsensical (in the middle of RAM), or we're doing something wrong in reading the address. It's possible we could learn something by booting Windows and seeing whether it uses the watchdog, and at what address. Something like the Device Manager or http://www.aida64.com/ could be useful. Here are some relevant registers from the RRG: 2.3 SMBus Module and ACPI Block 2.3.1 PCI Configuration Registers PCI_Reg 0x90 32 bits Smbus Base Address 2.3.2 SMBus Registers SMBUS register space defined by PCI config 0x90 2.3.3 Legacy ISA and ACPI Controller 2.3.3.1 Legacy Block Registers 2.3.3.1.1 IO-Mapped Control Registers IO_Reg 0xCD6 8 bits PM_Index (p. 163) IO_Reg 0xCD7 8 bits PM_Data 2.3.3.2 Power Management (PM) Registers (p. 165) PM_REG 0x69 8 bits WatchDogTimerControl (p. 190) PM_REG 0x6c 8 bits WatchDogTimerBase0 PM_REG 0x6d 8 bits WatchDogTimerBase1 PM_REG 0x6e 8 bits WatchDogTimerBase2 PM_REG 0x6f 8 bits WatchDogTimerBase3 2.3.4 WatchDogTimer Registers (p. 225) WD_Mem_Reg 0x00 32 bits WatchDogControl WD_Mem_Reg 0x04 32 bits WatchDogCount This is intertwined with piix4. I did notice that piix4_setup() reads the Smbus Base Address at PCI config offset 0x90, and it assumes I/O space. The SP5100 supports either MMIO or I/O, so if your system uses MMIO, things will go wrong. The attached patch checks for that. I haven't worked out the chain from there to the WatchDogTimerBase registers. Bjorn
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