Hi Lorenzo, Pali,
On 2021/07/23 18:36, Kunihiko Hayashi wrote:
Hi Pali,
[snip]
Just you need to specify that new/private IRQ domain into
irq_find_mapping() call.
I'll try to replace the events with new IRQ domain.
According to Pali's suggestion, the bridge handles INTX and it isn't difficult
to change IRQ's map for Root Port like the example.
It seems that it can't be applied to MSI.
On the other hand, according to Lorenzo's suggestion,
>>>>>>> IMO this should be modelled with a separate IRQ domain and chip for
>>>>>>> the root port (yes this implies describing the root port in the dts
>>>>>>> file with a separate msi-parent).
Interrupts for PME/AER event is assigned to number 0 of MSI IRQ domain.
(pcie_port_enable_irq_vec() in portdrv_core.c)
This expects MSI status bit 0 to be set when the event occurs.
However, in the uniphier PCIe controller, MSI status bit 0 is not set, but
the PME/AER status bit in the glue logic is set.
I think that it's hard to associate the new domain and "MSI-IRQ 0" event
if the new IRQ domain and chip is modelled.
So, I have no idea to handle both new IRQ domain and cascaded MSI event.
Is there any example for that?
Thank you,
---
Best Regards
Kunihiko Hayashi
