On Friday 23 July 2021 01:54:10 Kunihiko Hayashi wrote: > On 2021/07/18 9:51, Pali Rohar wrote: > > > > IMO this should be modelled with a separate IRQ domain and chip for > > > > the root port (yes this implies describing the root port in the dts > > > > file with a separate msi-parent). > > > > > > > > This series as it stands is a kludge. > > > > > > I see. However I need some time to consider the way to separate IRQ domain. > > > Is there any idea or example to handle PME/AER with IRQ domain? > > > > Seems that you are dealing with very similar issues as me with aardvark > > driver. > > > > As an inspiration look at my aardvark patch which setup separate IRQ > > domain for PME, AER and HP interrupts: > > https://lore.kernel.org/linux-pci/20210506153153.30454-32-pali@xxxxxxxxxx/ > > > > Thanks to custom driver map_irq function, it is not needed to describe > > root port with separate msi-parent in DTS. > > I need to understand your solution, though, this might be the same situation as my driver. I think it is very very similar as aardvark also returns zero as hw irq number (and it is not possible to change it). So simple solution for you is also to register separate IRQ domain for Root Port Bridge and then re-trigger interrupt with number 0 (which you wrote that is default) as: virq = irq_find_mapping(priv->irq_domain, 0); generic_handle_irq(virq); in your uniphier_pcie_misc_isr() function. There is no need to modify DTS. And also no need to use complicated logic for finding registered virq number via pcie_port_service_get_irq() and uniphier_pcie_port_get_irq() functions.
