Hi,
On Fri, May 20, 2011 at 4:49 AM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote:
> On Thu, May 19, 2011 at 5:12 PM, Benjamin Herrenschmidt
> <benh@xxxxxxxxxxxxxxxxxxx> wrote:
>> On Thu, 2011-05-19 at 11:58 -0600, Bjorn Helgaas wrote:
>>> The scan below PCIX0 (bus 0001:00) doesn't find anything. You really
>>> need a powerpc expert to help here, but in their absence, my guess
>>> would be something's wrong with config space access, so I would start
>>> by just adding some printks to ppc4xx_probe_pcix_bridge() to see if
>>> the rsrc_cfg address looks reasonable. You might need a chip spec or
>>> maybe you can compare it to the device tree (I have no idea what the
>>> relation between the device tree and OF is).
>>>
>>> You mentioned the u-boot "pci 2" command earlier. It found a device
>>> on bus 2, which means there must be at least one P2P bridge to get you
>>> from bus 0 to bus 2. So the output of "pci 0", "pci 1", "pci 80", and
>>> "pci 81" (to compare with what Linux found) would be interesting.
>>
>> Well, if it's PCIe, there's the "virtual" P2P bridge of the root
>> complex.
>>
>> The question is on what PCIe is his device connected, the one that we
>> see or the one that's disabled in the device-tree.
>
> I *think* the device Prashant is looking for ("02.00.00 0x1000
> 0x0072 Mass storage controller 0x00") is below the PCI-X bridge;
> at least the canyonlands.dts he posted says that PCIX0 leads to buses
> 0-3f.
>
Fixed the problem by soft resetting the PCIe port in the function
ppc460ex_pciex_port_init_hw().
Is it a right thing to do?
Following is the patch for kernel 2.6.38.4:
--------------------------------------------------------------------------------------
--- linux-2.6.38.4/arch/powerpc/sysdev/ppc4xx_pci.c.orig 2011-05-24
10:02:38.000000000 +0530
+++ linux-2.6.38.4/arch/powerpc/sysdev/ppc4xx_pci.c 2011-05-24
10:07:17.000000000 +0530
@@ -876,6 +876,20 @@
u32 val;
u32 utlset1;
+ switch (port->index)
+ {
+ case 0:
+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
+ mdelay(10);
+ break;
+ case 1:
+ mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST, 0x0);
+ mdelay(10);
+ break;
+ default:
+ break;
+ }
+
if (port->endpoint)
val = PTYPE_LEGACY_ENDPOINT << 20;
else
--------------------------------------------------------------------------------------
- Prashant
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