On Mon, May 10, 2021 at 04:15:06PM +0200, Lucas Stach wrote: > Starting with the i.MX7, arch PCIe instance has a differential refclk pad, > which can beused in multiple ways: > > - It's not used at all and the PHY reference clock is provided by a SoC > internal source, like on the previous SOCs. > - It's used as a clock input, for the board to provide a reference clock > for the PHY. > - It's used as a clock output, where the PHY reference clock is provided > by a SoC internal source and the same clock is also routed to the > refclk pad for consumption of board-level components. > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > index 308540df99ef..3ebd8553a818 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > @@ -38,6 +38,11 @@ Optional properties: > The regulator will be enabled when initializing the PCIe host and > disabled either as part of the init process or when shutting down the > host. > +- fsl,refclk-pad-mode: Usage mode of the refclk pad. Valid values: > + - 0: pad not used. PHY refclock is derived from SoC internal source. > + - 1: pad input. PHY refclock is provided externally via the refclk pad. > + - 2: pad output. PHY refclock is derived from SoC internal source and > + provided on the refclk pad. Seems like this belongs in the PHY's node? Or you could determine this based on the PHY's clock source. At least for the first 2 cases. Is there a known user for the 3rd case? If so, it's possible that what it's connected to needs a clock provider as well. Rob
