On Sunday 28 March 2021 16:09:12 Pali Rohár wrote: > > GIC > | > v > Aardvark TOP > | | | > v | v > ... | ... > | > v > +----+----+----+-- Aardvark CORE --+----+----+----+----+-- ... > | | | | | | | | | | | > v v v v v v v v | v v > PME ERR INTA INTB INTC INTD Link Hot | ... ... > Down Reset | > | > v > Aardvark MSI I have another question about PME, ERR, HP and Link interrupts. Normally kernel sees a real PCIe Root Bridge device on PCIe bus and this Root Bridge implements lot of functionality with INTx or MSI interrupts which are triggered when some PME, ERR, HP or other action happens. When INTx/MSI interrupts happens then pcie kernel drivers read from more PCIe status registers which action happened (PME, ERR, etc...). PCIe controller on Armada 37xx does not see any PCIe Root Bridge on the bus, there is directly only endpoint or upstream part of packet switch. Instead Armada 37xx provides registers which can be used to implement virtual/emulated PCIe Root Bridge. And now the issue is, when PME, ERR or any other action happens, GIC triggers interrupts and from aardvark CORE bits can be read which action happens. But because kernel pcie drivers for AER, PME or HP expects INTx/MSI interrupt, it is required to convert aardvark PME/ERR/... into INTA interrupt (because emulated bridge supports only INTx). Which means that specific action (e.g. ERR for AER) is now shared with all INTA interrupts and kernel needs to in chain call all drivers which uses shared INTA interrupt on IRQ domain for INTA. Which obviously degrades performance. Is there any way how to solve this issue without performance degradation? E.g. it is possible to allocate special IRQ INTx domain just for one particular PCIe device (that emulated PCIe Root Bridge)? So when PME or ERR interrupt happens, aardvark interrupt handler would convert it to INTA interrupt just for one device = Root Bridge.
