Hello!
I need some help with fixing interrupt handling in pci-aardvark.c
driver. If my understanding of HW is correct then whole interrupt
hierarchy for aardvark PCIe controller looks like this tree diagram:
GIC
|
v
Aardvark TOP
| | |
v | v
... | ...
|
v
+----+----+----+-- Aardvark CORE --+----+----+----+----+-- ...
| | | | | | | | | | |
v v v v v v v v | v v
PME ERR INTA INTB INTC INTD Link Hot | ... ...
Down Reset |
|
v
+----------------------------- Aardvark MSI ----------- ... ---------------+
| | |
v v v
+------+- MSI bit0 --+- .. -+ +------+- MSI bit1 --+- .. -+ +------+- MSI bit31 -+- .. -+
| | | | | | | | | | | | | | |
v v v v v v v v v v v v v v v
MSI MSI MSI ... MSI MSI MSI MSI ... MSI MSI MSI MSI ... MSI
0x0000 0x0020 0x0040 0xFFE0 0x0001 0x0021 0x0041 0xFFE1 0x001F 0x003F 0x005F 0xFFFF
Aardvark TOP interrupt is handled by advk_pcie_irq_handler() which then
calls advk_pcie_handle_int() for processing aardvark CORE interrupts and
then if summary MSI bit is set is called also advk_pcie_handle_msi().
When GIC triggers summary aardvark TOP interrupt then from aardvark HW I
can read which particular bits were set and therefore it is possible
that more interrupt happened. E.g. PME, ERR, INTB and MSI bit 4,5,8 can
be set at the same time. But for each MSI bit can be set only one final
16bit MSI interrupt number. So in interrupt handler I need to issue
callbacks for all those interrupts after mapping them to linux interrupt
numbers.
Aardvark HW allows to mask summary TOP, summary CORE, individual CORE
(PME, ERR, INTA, INTB, ...), summary MSI and individual MSI bits
interrupts, but not final 16 bit MSI interrupt number. MSI bits are low
5 bits of 16 bit interrupt number. So it is not possible to mask or
unmask MSI interrupt number X. It is possible to only mask/unmask all
MSI interrupts which low 5 bits is specific value.
Also aardvark HW allows to globally enable / disable processing of MSI
interrupts. Masking summary MSI interrupt just cause that GIC does not
trigger it but from registers I can read it (e.g. when GIC calls
aardvark interrupt handler for other non-MSI interrupt).
And I would like to ask, what is in this hierarchy from kernel point of
view "bottom part of MSI" and what is the "upper part of MSI"? As in
above diagram there are 3 MSI layers.
And which irq enable/disable/mask/unmask/ack callbacks I need to
implement for legacy irq, bottom MSI and upper MSI domains?
And where should I add code which globally enable/disable receiving of
aardvark MSI interrupts? Currently it is part of aardvark driver probe
function.
