On Tuesday 30 March 2021 16:34:47 Maciej W. Rozycki wrote: > On Tue, 30 Mar 2021, Pali Rohár wrote: > > > > If I were to implement this stuff, for good measure I'd give it a safety > > > margin beyond what the spec requires and use a timeout of say 2-4s while > > > actively querying the status of the device. The values given in the spec > > > are only the minimum requirements. > > > > Are you able to also figure out what is the minimal timeout value for > > PCIe Warm Reset? > > > > Because we are having troubles to "decode" correct minimal timeout value > > for this PCIe Warm Reset (not Function-level reset). > > The spec does not give any exceptions AFAICT as to the timeouts required > between the three kinds of a Conventional Reset (Hot, Warm, or Cold) and > refers to them collectively as a Conventional Reset across the relevant > parts of the document, so clearly the same rules apply. > > Maciej There are specified more timeouts related to Warm reset and PERST# signal. Just they are not in Base spec, but in CEM spec. See previous Amey's email where are described some timeouts and also links in my first email where I put other timeouts defined in specs relevant for PERST# signal and therefore also for Warm Reset.
