David Hagood wrote: > On Fri, 2011-03-11 at 13:45 -0800, Greg KH wrote: > > What was the response? > > Mostly "This always comes up when people do FPGAs and they always do it > wrong." > And when I asked "OK, so what is right?" <crickets_chirp.wav> > > There's nothing like "here's how an FPGA might trigger a hot plug > event." or "here's how your driver can trigger a hot plug event" or > anything like that. First you need the device configurable do have it configured ;) That can either be that it already loads a design on bootup (e.g. from SPI) or you use a non-FPGA bridge chip (e.g. one of those crappy PLX9656 things). For the in- FPGA thing you need something that comes up fast enough for the initial scan time limit (IIRC ~50ms or something like that). For Xilinx FPGAs they e.g. support "compressed bitstreams" so they can configure all identical blocks in parallel. If you leave the initial design mostly empty you can shrink the size of the bitstream and with it the configuration time to be small enough. For newer Xilinx chips (IIRC Spartan 6) there is even a solution directly from Xilinx doing exactly this. Coming up with a physically connected but PCI-wise dead board doesn't seem like a good idea to me as this basically gives you no benefit but makes accessing the device harder. Doing the hotplug thing later, well, I leave this to Greg to explain. Eike
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