Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC

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On 10/30/2020 3:33 AM, Jingoo Han wrote:
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On 10/29/20, 1:40 AM, Vidya Sagar wrote:

DesignWare core has a TLP digest (TD) override bit in one of the control
registers of ATU. This bit also needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a. This patch does the required programming in ATU upon
querying the system policy for ECRC.

Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
Reviewed-by: Jingoo Han <jingoohan1@xxxxxxxxx>

No, it should be Acked-by. I gave you Acked-by, not Reviewed-by.

Acked-by: Jingoo Han <jingoohan1@xxxxxxxxx>
Apologies. My bad. I saw the 'Reviewed-by' of the other patch (i.e. PCI/AER: Add pcie_is_ecrc_enabled() API) and put that for this patch as well. I'll update.



Best regards,
Jingoo Han

---
V3:
* Added 'Reviewed-by: Jingoo Han <jingoohan1@xxxxxxxxx>'

V2:
* Addressed Jingoo's review comment
* Removed saving 'td' bit information in 'dw_pcie' structure

  drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
  drivers/pci/controller/dwc/pcie-designware.h | 1 +
  2 files changed, 7 insertions(+), 2 deletions(-)

[...]




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