On Mon, Nov 29, 2010 at 08:59:00PM -0700, Matthew Wilcox wrote: > > Wouldn't the pxi -> bus extender -> pci -> bridge -> PCIe path involve > > more latency than the pxi -> bus extender -> PCIe path? > > Ah, I didn't realise what a PXI card was ... here's how I understand > the two options you have: > > root complex --> PCIe extender --> PXI card > root complex --> PCIe-PCI bridge --> PCI extender --> PXI card > > There's a PCIe-PCI bridge involved in both cases, but there's one fewer > bus segment involved if you're using the PCIe extender card. Could he use a PCIe bridge to have multiple PCIe devices downstream from root complex? e.g. like a PLX bridge? > > > The latency will all be in the setup. You only want to transfer 180 > > > bytes, and even the 33MHz, 32bit PCI bus can transfer that much data > > > in under two microseconds. > > > > Yes, that's what I expected. But what is a reasonable time for the > > setup? > > Hard to say; you need to figure out how the capture card is going to > notify the processing card that there's new data to be processed. Yeah, look at how common PCIe devices are programmed to do DMA to the host using either descriptor rings or scatter-gather lists. Then think about how the payload data will be generated and moved to the PCIe peer. It's not that different. Setup will be slightly different but the same basic principals apply. My guess is you'll need to DMA some control data as well to notify the peer that data has been transferred. Willy suggested this as well. At some point, the host will need to be involved again...but depending on the data rate and buffer sizes probably not that frequently. cheers, grant -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
