Hello, I am working on a PCI Express system based on ARM SoC with following setup: PCIe Root Complex -> PCIe-PCI Bridge -> PCI SATA Controller The numbering is: Bus #0 Device #0 = PCIe Root Complex (RC) Bus #1 Device #0 = PCIe-PCI Bridge Bus #2 Device #0 = PCI SATA Controller At the end of enumeration, the lspci shows the above devices correctly, but I observed that the PCIe RC and PCIe-PCI Bridge are not enabled (mem, bus mastering disabled). Now when I try to load the driver for SATA controller, it crashes as the memory access to SATA Controller's BAR window fails because the PCIe-PCI bridge is not enabled. I can force enabling the RC in my PCI controller code but the intermediate bridge(s) need to be enabled. If I do "echo 1 > /sys/bus/pci/rescan" before loading the SATA driver, the PCIe RC and Bridge are enabled and loading the SATA driver works fine. I am copying enumeration log below - enabling device for RC and PCI Bridge is only happening during rescan as seen form the log. Please let me know what I am missing here. Do I need to call pci_assign_unassigned_bridge_resources or pci_assign_unassigned_resources in my scan routine (after pci_scan_bus returns)? Thanks Hemant PCI Enumeration Log: ==================== pci_bus 0000:00: scanning bus pci 0000:00:00.0: found [104c:8888] class 000604 header type 01 pci 0000:00:00.0: calling pci_fixup_ide_bases+0x0/0x4c pci 0000:00:00.0: calling quirk_resource_alignment+0x0/0x19c pci_bus 0000:00: fixups for bus PCI: bus0: Fast back to back transfers disabled pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 0 pci 0000:00:00.0: bus configuration invalid, reconfiguring pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 1 pci_bus 0000:01: scanning bus pci 0000:01:00.0: found [10b5:8112] class 000604 header type 01 pci 0000:01:00.0: calling pci_fixup_ide_bases+0x0/0x4c pci 0000:01:00.0: calling quirk_resource_alignment+0x0/0x19c pci 0000:01:00.0: supports D1 pci 0000:01:00.0: PME# supported from D0 D1 D3hot pci 0000:01:00.0: PME# disabled pci_bus 0000:01: fixups for bus PCI: bus1: Fast back to back transfers disabled pci 0000:01:00.0: scanning [bus 00-00] behind bridge, pass 0 pci 0000:01:00.0: bus configuration invalid, reconfiguring pci 0000:01:00.0: scanning [bus 00-00] behind bridge, pass 1 pci_bus 0000:02: scanning bus pci 0000:02:00.0: found [1095:3124] class 000104 header type 00 pci 0000:02:00.0: reg 10: [mem 0x00000000-0x0000007f 64bit] pci 0000:02:00.0: reg 18: [mem 0x00000000-0x00007fff 64bit] pci 0000:02:00.0: reg 20: [io 0x0000-0x000f] pci 0000:02:00.0: reg 30: [mem 0x00000000-0x0007ffff pref] pci 0000:02:00.0: calling pci_fixup_ide_bases+0x0/0x4c pci 0000:02:00.0: calling quirk_resource_alignment+0x0/0x19c pci 0000:02:00.0: supports D1 D2 pci_bus 0000:02: fixups for bus PCI: bus2: Fast back to back transfers enabled pci_bus 0000:02: bus scan returning with max=02 pci_bus 0000:01: bus scan returning with max=02 pci_bus 0000:00: bus scan returning with max=02 pci 0000:00:00.0: fixup irq: got 48 pci 0000:01:00.0: fixup irq: got 48 pci 0000:02:00.0: fixup irq: got 48 pci 0000:00:00.0: BAR 8: assigned [mem 0x20000000-0x200fffff] pci 0000:00:00.0: BAR 9: assigned [mem 0x20100000-0x201fffff pref] pci 0000:00:00.0: BAR 7: can't assign io (size 0x1000) pci 0000:01:00.0: BAR 8: assigned [mem 0x20000000-0x200fffff] pci 0000:01:00.0: BAR 9: assigned [mem 0x20100000-0x201fffff pref] pci 0000:01:00.0: BAR 7: can't assign io (size 0x1000) pci 0000:02:00.0: BAR 6: assigned [mem 0x20100000-0x2017ffff pref] pci 0000:02:00.0: BAR 2: assigned [mem 0x20000000-0x20007fff 64bit] pci 0000:02:00.0: BAR 2: set to [mem 0x20000000-0x20007fff 64bit] (PCI address [ 0x20000000-0x20007fff] pci 0000:02:00.0: BAR 0: assigned [mem 0x20008000-0x2000807f 64bit] pci 0000:02:00.0: BAR 0: set to [mem 0x20008000-0x2000807f 64bit] (PCI address [ 0x20008000-0x2000807f] pci 0000:02:00.0: BAR 4: can't assign io (size 0x10) pci 0000:01:00.0: PCI bridge to [bus 02-02] pci 0000:01:00.0: bridge window [io disabled] pci 0000:01:00.0: bridge window [mem 0x20000000-0x200fffff] pci 0000:01:00.0: bridge window [mem 0x20100000-0x201fffff pref] pci 0000:00:00.0: PCI bridge to [bus 01-02] pci 0000:00:00.0: bridge window [io disabled] pci 0000:00:00.0: bridge window [mem 0x20000000-0x200fffff] pci 0000:00:00.0: bridge window [mem 0x20100000-0x201fffff pref] [...] pci 0000:00:00.0: calling quirk_cardbus_legacy+0x0/0x38 pci 0000:00:00.0: calling quirk_usb_early_handoff+0x0/0x548 pci 0000:01:00.0: calling quirk_cardbus_legacy+0x0/0x38 pci 0000:01:00.0: calling quirk_usb_early_handoff+0x0/0x548 pci 0000:02:00.0: calling quirk_cardbus_legacy+0x0/0x38 pci 0000:02:00.0: calling quirk_usb_early_handoff+0x0/0x548 PCI: CLS 32 bytes, default 32 [...] # echo 1 > /sys/bus/pci/rescan pci_bus 0000:00: scanning bus pci 0000:00:00.0: scanning [bus 01-02] behind bridge, pass 0 pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 1 pci_bus 0000:00: bus scan returning with max=00 pci 0000:01:00.0: PCI bridge to [bus 02-02] pci 0000:01:00.0: bridge window [io disabled] pci 0000:01:00.0: bridge window [mem 0x20000000-0x200fffff] pci 0000:01:00.0: bridge window [mem 0x20100000-0x201fffff pref] pci 0000:00:00.0: PCI bridge to [bus 01-02] pci 0000:00:00.0: bridge window [io disabled] pci 0000:00:00.0: bridge window [mem 0x20000000-0x200fffff] pci 0000:00:00.0: bridge window [mem 0x20100000-0x201fffff pref] PCI: enabling device 0000:00:00.0 (0140 -> 0143) pci 0000:00:00.0: enabling bus mastering PCI: enabling device 0000:01:00.0 (0140 -> 0143) pci 0000:01:00.0: enabling bus mastering # -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
