On 06/13/2010 11:38 PM, Maciej W. Rozycki wrote: > On Mon, 14 Jun 2010, Kenji Kaneshige wrote: > >> - Architectural limit of physical address in x86 32-bit mode is 40-bit >> (depnds on processor version). > > According to documentation I happen to have handy this limit is actually > 52 bits (and space is currently available in the data structures used for > a possible future extension up to 63 bits). > Yes. There are, however, very likely bugs in several classes due to incorrect bitmasks as well as 32-bit PFNs. We have made the decision based on data structure limitations (and just usability) to not support more than 2^36 bytes of RAM on 32 bits, but those data structures should not affect I/O. I;d like to track down and fix the bugs instead of papering over the problem... -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
