* Yinghai Lu wrote: > On Tue, Nov 17, 2009 at 12:47 AM, Thierry Reding > <thierry.reding@xxxxxxxxxxxxxxxxx> wrote: [...] > > dmesg (prefetchable and non-prefetchable cases) and lspci -tv output is > > attached. Perhaps I should give some more details about the setup: as can be > > seen from the lspci setup, there are three endpoints implemented in the FPGA, > > each behind its own bridge. All endpoints have all 6 BARs implemented, each > > BAR being 1MB non-prefetchable. For what it's worth, decreasing the BAR size > > to 64KB makes no difference. > > > > The odd thing, judging by the dmesg output, is that the bridges before the > > endpoints seem to get the correct configuration. Only for the endpoints does > > the BIOS seem to get things wrong. Dumping accesses to the BARs from within > > the FPGA shows that the BIOS indeed writes the correct bases to the endpoint > > registers (the bases nicely fitting into the window that the bridge is > > configured with) but then goes and overwrites those values with 0. > > > > Again, switching from non-prefetchable to prefetchable mode no longer exposes > > the issue as demonstrated by the second dmesg output. > > your BIOS doesn't assign some mmio [...] > [ 0.372217] pci 0000:04:00.0: reg 30 32bit mmio pref: [0x000000-0x0007ff] [...] > [ 0.488217] pci 0000:05:00.0: reg 30 32bit mmio pref: [0x000000-0x0007ff] [...] Thanks for that hint. I've finally been able to fix the problem. The reason was that the FPGA was missing proper handling for the expansion ROM base address register (30). Handling them just like normal BARs solves the issue. Thanks, Thierry -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
