Hi, I have a setup where an FPGA is connected to a PCIe port. The FPGA itself acts as a bridge and forwards PCI requests to some user logic that in turn simulates multiple PCIe endpoints. The communication between the root complex and the user logic works fine and all endpoints are visible to the BIOS and Linux later on. One problem that we're facing now is that during PCIe enumeration, the BIOS seems to correctly allocate and assign resources for all endpoints, but only if all BARs are designated prefetchable. If the BARs are configured as non-prefetchable, however, the BIOS still seems to allocate and assign resources correctly, but after the first assignment of base addresses, it decides to overwrite these with 0, except for the very first endpoint. Now when Linux comes up it reads those BARs and decodes them again, then writes the original 0 back. Therefore when the BARs are marked non-prefetchable, all endpoints except the first end up unusable in the system. Does anyone have an idea what might be going on here? Is there some restriction in PCIe that may be causing this behaviour? I've been going through the specification looking for clues but so far haven't come up with anything. Presuming I can't make the BIOS "do the right thing", is it possible to have the Linux kernel redo the PCIe enumeration and ignore the BIOS completely? Again I've been going through the code but all I've been able to find is those places where Linux checks the resources as allocated by the BIOS. There seems to be no code to override the BIOS. Thierry -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
