Shaohua Li wrote:
On Wed, Jul 22, 2009 at 09:15:22AM +0800, Kenji Kaneshige wrote:
Introduce 'aspm_capable' field to maintain the capable ASPM setting of
the link. By the 'aspm_capable', we don't need to recheck latency
every time ASPM policy is changed.
Each bit in 'aspm_capable' is associated to ASPM state (L0S/L1). The
bit is set if the associated ASPM state is supported by the link and
it satisfies the latency requirement (i.e. exit latency < endpoint
acceptable latency). The 'aspm_capable' is updated when
- an endpoint device is added (boot time or hot-plug time)
- an endpoint device is removed (hot-unplug time)
- PCI power state is changed.
- /*
- * Every switch on the path to root complex need 1
- * more microsecond for L1. Spec doesn't mention L0s.
- */
- l1_switch_latency += 1000;
- }
+ struct pcie_link_state *link = endpoint->bus->self->link_state;
+ while (link && state)
+ state &= link->aspm_capable;
this looks strange?
This is clearly a bug... Thank you for pointing this out.
Will fix in the next version.
Thanks,
Kenji Kaneshige
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