Re: [PATCH 7/7] PCI ASPM: support per direction l0s management

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On Wed, Jul 22, 2009 at 09:16:27AM +0800, Kenji Kaneshige wrote:
> The L0s state can be managed separately for each direction (upstream
> direction and downstream direction) of the link. But in the current
> implementation, those are mixed up. With this patch, L0s for each
> direction are managed separately.
> 
> To maintain three states (upstream direction L0s, downstream L0s and
> L1), 'aspm_support', 'aspm_enabled', 'aspm_capable', 'aspm_disable'
> and 'aspm_default' fields in struct pcie_link_state are changed to
> 3-bit from 2-bit. The 'latency' field is separated to two 'latency_up'
> and 'latency_dw' fields to maintain exit latencies for each direction
> of the link. For L0, 'latency_up.l0' and 'latency_dw.l0' are used to
> configure upstream direction L0s and downstream direction L0s
> respectively. For L1, larger value of 'latency_up.l1' and
> 'latency_dw.l1' is considered as L1 exit latency.
snip

> +
> +       /* Setup upstream direction L0s state */
> +       if (dwreg.support & PCIE_LINK_STATE_L0S)
> +               link->aspm_support |= ASPM_STATE_L0S_UP;
> +       if (dwreg.enabled & PCIE_LINK_STATE_L0S)
> +               link->aspm_enabled |= ASPM_STATE_L0S_UP;
> +       link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
> +
> +       /* Setup downstream direction L0s state */
> +       if (upreg.support & PCIE_LINK_STATE_L0S)
> +               link->aspm_support |= ASPM_STATE_L0S_DW;
> +       if (upreg.enabled & PCIE_LINK_STATE_L0S)
> +               link->aspm_enabled |= ASPM_STATE_L0S_DW;
> +       link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
> +
Somebody (from HP, IIRC) said a lot of systems don't implement one direction
L0S right if the other direction doesn't support it. And there is a recent
pcisig draft clarifies that software must not enable L0s in either direction
on a given link unless components on both sides of the link each support L0s.
Let's comfrom to it.

Thanks,
Shaohua
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