Shaohua Li wrote:
On Fri, Jun 26, 2009 at 10:59:20AM +0800, Kenji Kaneshige wrote:
Shaohua Li wrote:
On Fri, Jun 19, 2009 at 01:28:44PM +0800, Kenji Kaneshige wrote:
Shaohua Li wrote:
On Fri, Jun 19, 2009 at 11:19:49AM +0800, Kenji Kaneshige wrote:
Shaohua Li wrote:
On Fri, Jun 19, 2009 at 05:28:41AM +0800, Jesse Barnes wrote:
On Thu, 21 May 2009 11:10:06 +0900
Kenji Kaneshige <kaneshige.kenji@xxxxxxxxxxxxxx> wrote:
Hi,
This patch changes ASPM driver to enable more detailed ASPM
configuration. With this patch,
- ASPM can be enabled partially in the hierarchy.
- L0s can be managed for each direction (upstream direction and
downstream direction) of the link.
Well, these are nice features, but what kind of machine does you test?
Does it have several level hierarchy? The most powerful system I saw
just has two levels, which sounds not worth adding partial aspm.
Thank you very much for comments.
I think it is useful also for the system that doesn't have so
many levels of hierarchy, such as mobile systems. Here is "lspci -t"
output on my environment with some comments. My system also has
just two levels, but with the patch, upstream L0s is enabled on the
link 0000:15.00.0 (switch downstream port) to 0000:16:00.0 (endpoint)
in powersave mode.
Can you send me the output of lspci -vvvxxx please?
Here it is. Please note that I'm using pcie_aspm=force option.
Hi,
can you please split the patch into two patches, then I will have more detail
review/test. Also please don't do cleanup in the patches for new feature.
I had a simple look at the patch, and found at least one issue:
A link might have multiple child links, we need check all child links's latency to
enable the parent's ASPM. In pcie_config_aspm_path(), the patch seems not check
peer link.
My understanding is that we can enable parent ASPM even if one
or more child links don't meet the latency requirement and ASPM
is disabled on them. In this case, parent link will never enter
the upstream direction L0s nor L1 state because parent link's
downstream component (switch upstream port) never becomes idle.
Not sure about this. Microsoft's sides say switch's upstream link's
ASPM is always enabled in vista, which seems like what you said.
My understanding about this is from page 339 for L0s and page 342
for L1 of PCI Express spec 2.1.
By the way, though I don't know Microsoft's implementation, if it
always enables ASPM on switch's upstream link, the algorithm is
different from my patch. My patch disables ASPM on parent link
if it doesn't meet the latency requirement. If we always enable
ASPM on parent link, we cannot enable ASPM on the child link in
the following situation.
- parent link doesn't meet latency requirement
- child link meets latency requirement.
Thanks,
Kenji Kaneshige
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