Re: [patch 1/6] pci-quirks: unhide 'Overflow' device on i828{6,7}5P/PE chipsets

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On Wed, 11 Feb 2009 23:02:52 +0100
Micha__ Miros__aw <mirq-linux@xxxxxxxxxxxx> wrote:

> Hello,
> 
> Please use the following version of the patch. This version has shorter
> function names and message, and most importantly, better explanation
> of problem I encountered.
> 
> [patch starts below]
> 
> Some BIOSes hide 'overflow' device (dev #6) for i82875P/PE chipsets.
> The same happens for i82865P/PE. Add a quirk to enable this device.
> This allows i82875 EDAC driver to bind to chipset's dev #6 and not
> dev #0 as the latter is used by AGP driver.
> 
> On my laptop (i82865P based) ACPI code is disabling this device
> again in \_SB.PCI0._CRS method (called at least at PNP init time).
> This can be easily worked around by patching DSDT.
> 
> Signed-off-by: Micha__ Miros__aw <mirq-linux@xxxxxxxxxxxx>
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index a47db02..0ca02c7 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -1787,6 +1787,28 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
>  			PCI_DEVICE_ID_NX2_5709S,
>  			quirk_brcm_570x_limit_vpd);
>  
> +/* Originally in EDAC sources for i82875P:
> + * Intel tells BIOS developers to hide device 6 which
> + * configures the overflow device access containing
> + * the DRBs - this is where we expose device 6.
> + * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
> + */
> +static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
> +{
> +	u8 reg;
> +
> +	if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
> +		dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
> +		pci_write_config_byte(dev, 0xF4, reg | 0x02);
> +	}
> +}
> +
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
> +                        quirk_unhide_mch_dev6);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
> +                        quirk_unhide_mch_dev6);
> +
> +
>  #ifdef CONFIG_PCI_MSI
>  /* Some chipsets do not support MSI. We cannot easily rely on setting
>   * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually

Where do we stand with Jesse's earlier comment?

On Fri, 9 Jan 2009 13:40:02 -0800
Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> wrote:
> 
> This one already got a NAK until Michal can figure out a way to prevent the 
> SMM code on his machine from hiding this device periodically.


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