[patch 1/6] pci-quirks: unhide 'Overflow' device on i828{6,7}5P/PE chipsets

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From: Michal Miroslaw <mirq-linux@xxxxxxxxxxxx>

As I found out from EDAC driver sources for i82875P some BIOSes for
i82875P/PE hide 'overflow' device 6.  The same thing happens for
i82865P/PE chipsets.

After testing this patch for couple of days on my laptop (i82856P) it
looks like something is resetting device 0 (MCH) config register 0xF4 to
zero and effectively disabling the device again.  The delay looks random
to me.  I can easily update the register using 'hexedit
/sys/bus/pci/devices/0000\:00\:00.0/config' and see correct values in
lspci output afterwards.

On Fri, 9 Jan 2009 13:40:02 -0800
Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> wrote:
> 
> This one already got a NAK until Michal can figure out a way to prevent the 
> SMM code on his machine from hiding this device periodically.

[akpm@xxxxxxxxxxxxxxxxxxxx: coding-style fixes]
Signed-off-by: Michal Miroslaw <mirq-linux@xxxxxxxxxxxx>
Cc: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
Cc: Doug Thompson <norsk5@xxxxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>
---

 drivers/pci/quirks.c |   23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff -puN drivers/pci/quirks.c~pci-quirks-unhide-overflow-device-on-i828675p-pe-chipsets drivers/pci/quirks.c
--- a/drivers/pci/quirks.c~pci-quirks-unhide-overflow-device-on-i828675p-pe-chipsets
+++ a/drivers/pci/quirks.c
@@ -2149,6 +2149,29 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AT
 
 #endif /* CONFIG_PCI_MSI */
 
+/* Originally in EDAC sources for i82875P:
+ * Intel tells BIOS developers to hide device 6 which
+ * configures the overflow device access containing
+ * the DRBs - this is where we expose device 6.
+ * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
+ */
+static void __devinit
+quirk_unhide_mch_memory_controller_dev6(struct pci_dev *dev)
+{
+	u8 reg;
+
+	if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
+		dev_info(&dev->dev,
+			"Enabling MCH Memory Controller 'Overflow' Device");
+		pci_write_config_byte(dev, 0xF4, reg | 0x02);
+	}
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
+			quirk_unhide_mch_memory_controller_dev6);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
+			quirk_unhide_mch_memory_controller_dev6);
+
 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
 			  struct pci_fixup *end)
 {
_
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