As I found out from EDAC driver sources for i82875P some BIOSes for i82875P/PE hide 'overflow' device 6. The same thing happens for i82865P/PE chipsets. After testing this patch for couple of days on my laptop (i82856P) it looks like something is resetting device 0 (MCH) config register 0xF4 to zero and effectively disabling the device again. The delay looks random to me. I can easily update the register using 'hexedit /sys/bus/pci/devices/0000\:00\:00.0/config' and see correct values in lspci output afterwards. Signed-off-by: Michał Mirosław <mirq-linux@xxxxxxxxxxxx> diff -urN linux-2.6.27.7-brfix1-nvpid/drivers/pci/quirks.c pci-quirks/drivers/pci/quirks.c --- linux-2.6.27.7-brfix1-nvpid/drivers/pci/quirks.c 2008-10-10 00:13:53.000000000 +0200 +++ pci-quirks/drivers/pci/quirks.c 2008-12-06 22:18:46.000000000 +0100 @@ -2007,3 +2008,25 @@ quirk_msi_intx_disable_bug); #endif /* CONFIG_PCI_MSI */ + +/* Originally in EDAC sources for i82875P: + * Intel tells BIOS developers to hide device 6 which + * configures the overflow device access containing + * the DRBs - this is where we expose device 6. + * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm + */ +static void __devinit quirk_unhide_mch_memory_controller_dev6(struct pci_dev *dev) +{ + u8 reg; + + if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { + dev_info(&dev->dev, "Enabling MCH Memory Controller 'Overflow' Device"); + pci_write_config_byte(dev, 0xF4, reg | 0x02); + } +} + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, + quirk_unhide_mch_memory_controller_dev6); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, + quirk_unhide_mch_memory_controller_dev6); + -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
