On Tue, 9 Dec 2008, Grant Grundler wrote:
On Tue, Dec 09, 2008 at 10:32:15PM +1100, Timothy S. Nelson wrote:
On Mon, 8 Dec 2008, Alex Villac??s Lasso wrote:
The SATA ROM example is from my work machine, where the SATA hard disk is
already a boot device. Why is this not a proper example of the PCI ROM
reading failure?
I think he's saying that he thinks both are failures, but that they have
different causes, or possibly that getting a secondary VGA card working can
be done in a way that doesn't work for other devices. I could be wrong,
but that's how I interpret what I read.
Yes, that's almost what I meant. I meant getting a secondard VGA card working
has additional issues that SATA cards won't have. The SATA Expansion ROM
issue might happen to be the same thing but I wouldn't assume that.
VGA is "special" (as in horribly crippled by historical precedent).
SATA is not. Additional "MMIO routing" magic happens for VGA devices
in the PCI Host bus controllers and PCI-PCI Bridges. ISTR the BIOS
also needs to be at a fixed location. If I've got that right, given
a "fixed location" would mean only one VGA device can have it's
Expansion ROM enabled at a time.
Can someone with x86 VGA routing experience confirm? Bjorn Helgaas?
No experience, and unfortunately only a vague idea of what we're
discussing here (my skills at this low level of software skills haven't been
used since the days of CGA monitors). But I have some clarifying information.
Firstly, the code that's causing the trouble in Xorg (that is trying
to read the ROM) is only ever called on a machine with the second graphics
card enabled. So the first graphics card doesn't need to call this.
To illustrate my second point, I'll post some selected output of lspci:
------------------------------------------------------------
01:00.0 VGA compatible controller: nVidia Corporation NV17 [GeForce4 MX 440]
(rev a3) (prog-if 00
[VGA controller])
Subsystem: Micro-Star International Co., Ltd. Device 8470
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 10
Region 0: Memory at f0000000 (32-bit, non-prefetchable) [disabled] [size=16M]
Region 1: Memory at e0000000 (32-bit, prefetchable) [disabled] [size=128M]
Region 2: Memory at e8000000 (32-bit, prefetchable) [disabled] [size=512K]
[virtual] Expansion ROM at e8080000 [disabled] [size=128K]
Capabilities: <access denied>
Kernel modules: nvidiafb, rivafb
02:02.0 VGA compatible controller: Silicon Integrated Systems [SiS] 86C326
5598/6326 (rev 0b) (pr
og-if 00 [VGA controller])
Subsystem: Palit Microsystems Inc. SiS6326 GUI Accelerator
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB
2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR-
<PERR- INTx-
Latency: 32 (500ns min)
Interrupt: pin A routed to IRQ 11
Region 0: Memory at f4000000 (32-bit, prefetchable) [size=8M]
Region 1: Memory at f3000000 (32-bit, non-prefetchable) [size=64K]
Region 2: I/O ports at 9800 [size=128]
[virtual] Expansion ROM at f2030000 [disabled] [size=64K]
Capabilities: <access denied>
------------------------------------------------------------
Now, I invite you to note that there are two expansion ROMs listed,
and they have different addresses.
Note that these are taken from a running Xserver; specifically the SiS
card is currently being used.
Anyway, I hope some of this information helps :). I should mention
that I'm not the guy who sent in the ticket, merely someone who wants it
fixed, but hasn't had a chance to look at it properly yet (and, at least
compared to Alex Villacis-Lasso, and probably many others, doesn't have the
level of skills); in the meantime, though, I want to help the communication
all I can.
:)
---------------------------------------------------------------------
| Name: Tim Nelson | Because the Creator is, |
| E-mail: wayland@xxxxxxxxxxxxx | I am |
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