On Sun, Oct 05, 2008 at 07:24:42PM -0700, Randy Dunlap wrote:
> From: Randy Dunlap <randy.dunlap@xxxxxxxxxx>
>
> Spell "Signaled" like the PCI SIG spells it (not Signalled).
Can I propose an alternative patch? I don't have a problem with
Randy's, but since we already use "MSI-X" for that capability, maybe we
should use "MSI" for this one? It brings that line back down below 80
columns, which is nice.
I further wonder if we want to report 'Enable' and 'Mask' in the same
order ... and 'Count' certainly seems like a better name than 'TabSize'.
----
From: Matthew Wilcox <willy@xxxxxxxxxxxxxxx>
Change the spelling of 'Signalled' to 'Signaled' to match the PCI spec.
Report the capability as 'MSI' instead of either 'Message Signaled
Interrupts' to fit better with MSI-X and bring the width of this line
below 80 columns.
Inspired-by: Randy Dunlap <randy.dunlap@xxxxxxxxxx>
Signed-off-by: Matthew Wilcox <willy@xxxxxxxxxxxxxxx>
--- pciutils-3.0.2.orig/lib/header.h
+++ pciutils-3.0.2/lib/header.h
@@ -187,7 +187,7 @@
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
-#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
+#define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
@@ -287,7 +287,7 @@
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
-/* Message Signalled Interrupts registers */
+/* Message Signaled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */
#define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */
--- pciutils-3.0.2.orig/lspci.c
+++ pciutils-3.0.2/lspci.c
@@ -922,7 +922,7 @@ cap_msi(struct device *d, int where, int
u32 t;
u16 w;
- printf("Message Signalled Interrupts: Mask%c 64bit%c Count=%d/%d Enable%c\n",
+ printf("MSI: Mask%c 64bit%c Count=%d/%d Enable%c\n",
FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
FLAG(cap, PCI_MSI_FLAGS_64BIT),
1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
--- pciutils-3.0.2.orig/tests/cap-pcie-1
+++ pciutils-3.0.2/tests/cap-pcie-1
@@ -10,7 +10,7 @@
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Subsystem: Device 8086:0000
- Capabilities: [60] Message Signalled Interrupts: Mask+ 64bit- Queue=0/1 Enable+
+ Capabilities: [60] MSI: Mask+ 64bit- Count=1/2 Enable+
Address: fee00000 Data: 40b0
Masking: 00000003 Pending: 00000000
Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00
--- pciutils-3.0.2.orig/tests/cap-pcie-2
+++ pciutils-3.0.2/tests/cap-pcie-2
@@ -11,7 +11,7 @@
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=1 PME-
- Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/0 Enable-
+ Capabilities: [50] MSI: Mask+ 64bit+ Count=0/1 Enable-
Address: 0000000000000000 Data: 0000
Masking: 00000000 Pending: 00000000
Capabilities: [70] MSI-X: Enable+ Mask- TabSize=10
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
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