On 20/04/2023 9:32 am, Thomas Gleixner wrote: > On Wed, Apr 19 2023 at 17:21, Andrew Cooper wrote: >> On 19/04/2023 2:50 pm, Andrew Cooper wrote: >> For xAPIC, the APIC_ID register is writeable (at least, model >> specifically), and CPUID is only the value it would have had at reset. >> So the AP bringup logic can't actually use CPUID reliably. >> >> This was changed in x2APIC, which made the x2APIC_ID immutable. >> >> I don't see an option other than the AP bringup code query for xAPIC vs >> x2APIC mode, and either looking at the real APIC_ID register, or falling >> back to CPUID. > I'm pondering to simply deny parallel mode if x2APIC is not there. I'm not sure if that will help much. Just because x2APIC is there doesn't mean it's in use. There are several generations of Intel system which have x2APIC but also use the opt-out bit in ACPI tables. There are some machines which have mismatched APIC-ness settings in the BIOS->OS handover. There's very little you can do on the BSP alone to know for certain that the APs come out of wait-for-SIPI already in x2APIC mode. One way is the ÆPIC Leak "locked into x2APIC mode" giant security bodge. If the system really does have a CPU with an APIC ID above 0xfe, then chances are good that the APs come out consistently... ~Andrew
