On Wed, Apr 19 2023 at 17:21, Andrew Cooper wrote: > On 19/04/2023 2:50 pm, Andrew Cooper wrote: >> What I'm confused by is why this system boots in the first place. I can >> only think that's is a system which only has 4-bit APIC IDs, and happens >> to function when bit 4 gets truncated off the top of the SIPI destination... > > https://www.amd.com/system/files/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf > > This system does still require the IO-APICs to be at 0, and the LAPICs > to start at some offset, which is clearly 16 in this case. Also, this > system has configurable 4-bit or 8-bit wide APIC IDs, and I can't tell > which mode is active just from the manual. That document contradicts itself: "The ApicId of core j must be enumerated/assigned as: ApicId[core=j] = (OFFSET_IDX) * MNC + j Where OFFSET_IDX is an integer offset (0 to N) used to shift up the core ApicId values to allow room for IOAPIC devices. It is recommended that BIOS use the following APIC ID assignments for the broadest operating system sup- port. Given N = MNC and M = Number_Of_IOAPICs: • Assign the core ApicId’s first from 0 to N-1, and the IOAPIC IDs from N to N+(M-1)." Oh well. If the rest of these docs is of the same quality then it's not a surprise that BIOSes are trainwrecks. > But, it does mean that the BIOS has genuinely modified the APIC IDs of > the logic processors. This does highlight an error in reasoning with > the parallel bringup code. Yes. > For xAPIC, the APIC_ID register is writeable (at least, model > specifically), and CPUID is only the value it would have had at reset. > So the AP bringup logic can't actually use CPUID reliably. > > This was changed in x2APIC, which made the x2APIC_ID immutable. > > I don't see an option other than the AP bringup code query for xAPIC vs > x2APIC mode, and either looking at the real APIC_ID register, or falling > back to CPUID. I'm pondering to simply deny parallel mode if x2APIC is not there. Thanks, tglx
