Add the ALT_COND_RUN_ON_PA1X alternative conditional to nop
out a 64-bit ldd instruction in prefetchw() when running on 32-bit CPUs.
Signed-off-by: Helge Deller <deller@xxxxxx>
diff --git a/arch/parisc/include/asm/alternative.h b/arch/parisc/include/asm/alternative.h
index 0ec54f43d6d2..8b94aa4f1bd7 100644
--- a/arch/parisc/include/asm/alternative.h
+++ b/arch/parisc/include/asm/alternative.h
@@ -9,6 +9,7 @@
#define ALT_COND_NO_SPLIT_TLB 0x08 /* if split_tlb == 0 */
#define ALT_COND_NO_IOC_FDC 0x10 /* if I/O cache does not need flushes */
#define ALT_COND_RUN_ON_QEMU 0x20 /* if running on QEMU */
+#define ALT_COND_RUN_ON_PA1X 0x40 /* if running on PA1.x CPU */
#define INSN_PxTLB 0x02 /* modify pdtlb, pitlb */
#define INSN_NOP 0x08000240 /* nop */
diff --git a/arch/parisc/include/asm/prefetch.h b/arch/parisc/include/asm/prefetch.h
index 6e63f720024d..ea898362dfc0 100644
--- a/arch/parisc/include/asm/prefetch.h
+++ b/arch/parisc/include/asm/prefetch.h
@@ -17,6 +17,8 @@
#define __ASM_PARISC_PREFETCH_H
#ifndef __ASSEMBLY__
+#include <asm/alternative.h>
+
#ifdef CONFIG_PREFETCH
#define ARCH_HAS_PREFETCH
@@ -35,7 +37,9 @@ static inline void prefetch(const void *addr)
#define ARCH_HAS_PREFETCHW
static inline void prefetchw(const void *addr)
{
- __asm__("ldd 0(%0), %%r0" : : "r" (addr));
+ __asm__("ldd 0(%0), %%r0"
+ ALTERNATIVE(ALT_COND_RUN_ON_PA1X, INSN_NOP)
+ : : "r" (addr));
}
#endif /* CONFIG_PA20 */
diff --git a/arch/parisc/kernel/alternative.c b/arch/parisc/kernel/alternative.c
index daa1e9047275..276904ab7265 100644
--- a/arch/parisc/kernel/alternative.c
+++ b/arch/parisc/kernel/alternative.c
@@ -33,6 +33,7 @@ void __init_or_module apply_alternatives(struct alt_instr *start,
((cache_info.dc_size == 0) ? ALT_COND_NO_DCACHE : 0) |
((cache_info.ic_size == 0) ? ALT_COND_NO_ICACHE : 0) |
(running_on_qemu ? ALT_COND_RUN_ON_QEMU : 0) |
+ ((boot_cpu_data.cpu_type < pcxu) ? ALT_COND_RUN_ON_PA1X : 0) |
((split_tlb == 0) ? ALT_COND_NO_SPLIT_TLB : 0) |
/*
* If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit
