On Tue, 2022-04-19 at 17:29 -0400, John David Anglin wrote: > We know that the PDC call to determine cache > characteristics indicates that the alias boundary on PA8800/PA8900 is > larger than 16 MB. Sorry, late to the party. What the PDC tells you is unreliable. However, the Architecture guide Appendix F says "These rules provide offset aliasing on 16 Mbyte boundaries, with optional support for offset aliasing on smaller power of two sized boundaries, and either restricted or unlimited space aliasing." So unless someone has an update to the architecture guide, 16MB as a cache stride is architecturally required to work. The tmpalias code in pacache.S is predicated on an assurance by the old HP chip designers that no chip was released with a cache stride greater than 4MB, meaning we could safely relax the 16MB architectural rules down to 4MB. James
