Hi Sven,
On 10/10/21 21:36, Sven Schnelle wrote:
> Helge Deller <deller@xxxxxx> writes:
>
>> On 10/10/21 20:38, Sven Schnelle wrote:
>>> +void notrace toc_intr(struct pt_regs *regs)
>>> +{
>>> + struct pdc_toc_pim_20 pim_data20;
>>> + struct pdc_toc_pim_11 pim_data11;
>>> +
>>> + nmi_enter();
>>> +
>>> + if (boot_cpu_data.cpu_type >= pcxu) {
>>
>> I wonder if this is correct.
>> If we boot a 32bit-kernel on a 64-bit (pcxu) machine, then
>> I think the code below for pdc_pim_toc11() should be executed.
>> So, maybe we need a #ifdef CONFIG_64BIT above...
>>
>>
>>> + if (pdc_pim_toc20(&pim_data20))
>>> + panic("Failed to get PIM data");
>>> + toc20_to_pt_regs(regs, &pim_data20);
>>> + } else {
>>
>> ... with an #else here
>>
>>> + if (pdc_pim_toc11(&pim_data11))
>>> + panic("Failed to get PIM data");
>>> + toc11_to_pt_regs(regs, &pim_data11);
>>> + }
>>
>> and #endif here. ??
>
> Hmm, that's what i understood from the HPMC PIM code,
> transfer_pim_to_trap_frame(). If it's running a 32 Bit OS, than PDC
> returns a wide frame on a 64 bit capable CPU? But maybe i have to read
> the documentation/code again.
No, that seems correct.
On a 64bit machine even a 32bit kernel seems to get the 64bit register PIM data:
64bit kernel:
[0]kdb> rd
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.15.0-rc5-64bit+ #1218
Hardware name: 9000/785/C3700
YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI
PSW: 00001000000001001111001000001111 Not tainted
r00-03 000000ff0804f20f 0000000040c45720 0000000040b6dd40 0000000040f004e0
r04-07 0000000040c1c720 0000000040f004b0 0000000040f14608 0000000000000004
r08-11 0000000000000001 0000000040c45720 0000000040c45720 0000000000000003
r12-15 0000000000000000 000000004111f020 0000000040fc7810 0000000040c3cf20
r16-19 0000000040c3cf20 0000000040f00240 0000000040f00240 4000000000000000
r20-23 0000000000000008 0000000000000000 0000000000000000 0000000000000000
r24-27 0000000000000000 0000000000000000 000000000000f45c 0000000040c1c720
r28-31 0000000000000000 0000000040f00530 0000000040f00560 0000000000000004
sr00-03 0000000000000400 0000000000000000 0000000000000000 0000000000000400
sr04-07 0000000000000000 0000000000000000 0000000000000000 0000000000000000
IASQ: 0000000000000000 0000000000000000 IAOQ: 0000000040b6dd5c 0000000040b6dd60
IIR: 503c0b00 ISR: 0000000000000000 IOR: 0000000000000000
CPU: 0 CR30: 0000000040f00000 CR31: 00000000ffff55ff
ORIG_R28: 0000000000000000
IAOQ[0]: cpu_idle_poll.isra.0+0x94/0x100
IAOQ[1]: cpu_idle_poll.isra.0+0x98/0x100
Backtrace:
[<0000000040287490>] do_idle+0x1d8/0x290
[<00000000402877a4>] cpu_startup_entry+0x7c/0x88
[<0000000040b65ff8>] rest_init+0x220/0x248
[<0000000040100ffc>] arch_call_rest_init+0x2c/0x40
32bit Kernel:
kdb> rd
CPU: 0 PID: 0 Comm: swapper Not tainted 5.15.0-rc5-32bit+ #804
Hardware name: 9000/785/C3700
YZrvWESTHLNXBCVMcbcbcbcbOGFRQPDI
PSW: 00000000000001001111111100001111 Not tainted
r00-03 0004ff0f 10a03cb0 1079506c 109fd280
r04-07 00000004 10a03cb0 11e01d1a 10a03cb0
r08-11 00000000 10a06cdc 1090ea5c 10aa0cb0
r12-15 1090ea5c ffffffff 00000000 f0400004
r16-19 f0000884 f000017c f0000174 00000004
r20-23 0000000f 00000000 101c0704 00000009
r24-27 84cf5d16 109fd000 10a16f20 109474b0
r28-31 00000001 84cf7ca2 109fd2c0 101b773c
sr00-03 00000000 0000001d 00000000 0000001d
sr04-07 00000000 00000000 00000000 00000000
IASQ: 00000000 00000000 IAOQ: 1079508c 10795090
IIR: e800001a ISR: 00000000 IOR: 00000000
CPU: 0 CR30: 109fd000 CR31: ffff55ff
ORIG_R28: 00000000
IAOQ[0]: cpu_idle_poll.isra.0+0x38/0x50
IAOQ[1]: cpu_idle_poll.isra.0+0x3c/0x50
RP(r2): cpu_idle_poll.isra.0+0x18/0x50
Backtrace:
[<101bd500>] do_idle+0x88/0xd8
[<101bd6fc>] cpu_startup_entry+0x20/0x24
[<1078f14c>] rest_init+0xb0/0xc4
[<10102820>] 0x10102820
Your patch is correct.
Helge
