Hi List, On Fri, May 24, 2019 at 12:50:03PM +0200, Sven Schnelle wrote: > On Fri, May 24, 2019 at 08:58:50AM +0200, Sven Schnelle wrote: > > Hi List, > > > > i recently got my hands on an old C240. I see a Kernel oops pretty early when > > alternatives patching is enabled: > > [..] > > My (wild) guess is that we're patching away some memory barrier or cache flush > > so the SCRIPTS engine in the SCSI controller starts executing garbage and triggers > > a PCI bus read/write to an invalid address. The reason the INB() is given as the > > HPMC location is likely caused by the delay between writing DSPS and the chip actually > > starting to fetch insn/data. > > > > Does that ring any bell for someone on the list? Otherwise i can check the > > alternatives patching over the weekend, i think there are not that many locations. > > > > The good thing is it's reproducible - it always crashes. Either in SCSI or in > > Tulip. > > Did a quick test, removing ALT_COND_N_IOC_FDC from asm_io_fdc() seems to fix this > issue. Haven't looked in more detail into this though. Added some debugging: [ 25.405365] boot_cpu_data.pdc_capabilities: 2 So PDC says IO-PDIR fetches are not performed coherently, *BUT*: When this bit is clear, flushes and syncs are not required. This bit is only applicable to SBAs, and does not apply to Legacy IOAs. With my limited understand i would think that C240 has a 'Legacy IOA' while C3xxx has SBA? So i think we would need to add some check whether we have an IOA or SBA in the alternatives code? Sven
