On Fri, May 24, 2019 at 08:58:50AM +0200, Sven Schnelle wrote:
> Hi List,
>
> i recently got my hands on an old C240. I see a Kernel oops pretty early when
> alternatives patching is enabled:
> [..]
> My (wild) guess is that we're patching away some memory barrier or cache flush
> so the SCRIPTS engine in the SCSI controller starts executing garbage and triggers
> a PCI bus read/write to an invalid address. The reason the INB() is given as the
> HPMC location is likely caused by the delay between writing DSPS and the chip actually
> starting to fetch insn/data.
>
> Does that ring any bell for someone on the list? Otherwise i can check the
> alternatives patching over the weekend, i think there are not that many locations.
>
> The good thing is it's reproducible - it always crashes. Either in SCSI or in
> Tulip.
Did a quick test, removing ALT_COND_N_IOC_FDC from asm_io_fdc() seems to fix this
issue. Haven't looked in more detail into this though.
index 73ca89a47f49..d83b1adf2f3f 100644
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -52,7 +52,6 @@ void parisc_setup_cache_timing(void);
#define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
- ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
: : "r" (addr) : "memory")
#define asm_io_sync() asm volatile("sync" \
ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
Sven
