On Sat, 2019-04-06 at 16:40 -0400, Mikulas Patocka wrote: > > On Sat, 6 Apr 2019, James Bottomley wrote: > > > On Sat, 2019-04-06 at 16:13 -0400, Mikulas Patocka wrote: > > > > > > > Of course, on systems without a merced bus, we don't need the > lock > > > at > > > > all, so runtime patching might be usable to fix that case. > > > > > > > > James > > > > > > The lock is still needed to synchronize TLB fault handlers with > the > > > code that modifies the pagetables - but we could have per-process > > > lock for this purpose. > > > > It is? I don't think we need any per-arch sync for that. The > purge > > should happen after all modifications are done so the next page > fault > > inserts the new TLB entry ... so if there is a place where the > purge > > lock matters to the page table updates, we're doing something > wrong. > > > > James > > Suppose that this sequence happens: > > CPU1: > (inside the TLB miss handler) > read the value XXX from the pagetables to the register > > CPU2: > modify the value in the pagetables to YYY > broadcast a TLB purge > > CPU1: > receives the TLB purge broadcast and flushes the TLB > ... continues executing the TLB handler and inserts the value XXX > from the register into the TLB > > And now, CPU1 is running with stale entry in the TLB. We need the > lock to prevent this situation. Heh, this is the dreaded appendix F. In general, if we're executing a high priority interruption for a TLB miss, the address is termed relied upon, so a purge for the same address won't be acted upon and acknowledged by the CPU until we leave the high priority handler (and have thus either inserted a TLB entry or dropped into full fault handling). This effectively makes the purge and the insertion atomic with respect to each other as they would be if the CPU had a hardware TLB miss handler. In the worst case, the CPU refaults on the same address because it got inserted then purged and the new translation then gets inserted second time around. James
