On Sun, 2015-09-27 at 12:07 -0400, John David Anglin wrote: > On 2015-09-26, at 11:38 AM, John David Anglin wrote: > > > The attached change reduces L1_CACHE_BYTES from 32 on PA1.1 and 64 on PA2.0 to 16. > > > > This is based on examination of the L1 cache design for the PA-8700 processor where it can > > be seen the processor loads two double words per cycle. This line length is consistent with the > > original alignment requirement for the ldcw instruction. > > > > Thus, we need to distinguish between the L1 and L2 (SMP) cache line lengths. > > > > The attached change bumps SMP_CACHE_BYTES to 128 bytes as this is the line length used > > on PA-8800 and PA-8900 processors. This increases the overall kernel size somewhat but seems > > logically correct. > > > Slight tweak to previous. This version only bumps SMP_CACHE_BYTES when CONFIG_SMP > is defined. What makes you think we need SMP_CACHE_BYTES to be different from L1_CACHE_BYTES? No other architecture does this. The theory that gives us two defines was that some SMP systems would arbitrate for memory at geater than cache line offsets but, in practise, none does because that's the level at which the cross CPU memory ownership model works anyway. James -- To unsubscribe from this list: send the line "unsubscribe linux-parisc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
