Grant Grundler wrote:
[snip]
PS: in this doc feb96a6.pdf (easy to find) it was said:
"[snip]
Entries in the PA 7200 and PA 8000 caches are stored in lines
of 32 bytes.
[snip]
Because one-word writes occur in the I/O system, for registers,
semaphores, or short DMA writes it was necessary that the I/O
adapter implement a one-line-deep cache to buffer cache lines,
so that these one-word writes could be executed by performing
a coherent read private transaction on the Runway bus, obtaining
the most recent copy of the cache line, modifying it locally in
cache, and finally writing the modified line back to main memory.
...
2 thinks:
- it seems to confirm that cache line is well 32bytes wide ;-)
- for 'one word writes...' how should it be implemented?
"one word writes" refers to DMA writes, not CPU writes.
(tx it's not always easy to follow the master and the slave in this story)
It look like the sba_iommu driver:
"READ_REG(ioc-ioc_ha_IOC_PCOM); /* flush purges */
but without more detailed docs on U2/UTurn ccio, I don't know how to
implement matter, sorry.
The IOMMU driver programs the IO Pdir with the results of "lci" instruction
and this should be all the IOMMU needs to coherently read/modify/write
the cacheline that the "one word" DMA write is targeting. In short,
it's already implemented or I'd think we'd see much worse problems
on ccio platforms.
hth,
grant
Ok.
Just one thought because in the backport I did on ccio of your job on sba (which seems to works for me as well as previous
stuff, may be a bit better for system low in ram like my c110), it was one of the matter related to io coherency which I
didn't reach to backport?
Tx again,
r.
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