On Wed, Mar 12, 2008 at 10:16:29AM +0100, rubisher wrote:
...
> mmm follwing stuff shouldn't so be enough:
> Index: b/drivers/parisc/ccio-dma.c
> ===================================================================
> --- a/drivers/parisc/ccio-dma.c 2008-03-12 08:49:20.000000000 +0000
> +++ b/drivers/parisc/ccio-dma.c 2008-03-12 08:50:54.000000000 +0000
> @@ -624,7 +624,8 @@
> ** the real mode coherence index generation of U2, the PDIR entry
> ** must be flushed to memory to retain coherence."
> */
> - asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
> + asm volatile("fdc %%r0(%0)" : : "r" (&pdir_ptr[1]));
> + asm volatile("fdc %%r0(%0)" : : "r" (&pdir_ptr[0]));
NACK
> asm volatile("sync");
> }
>
> @@ -695,7 +696,7 @@
> ** Hopefully someone figures out how to patch (NOP) the
> ** FDC/SYNC out at boot time.
> */
> - asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr[7]));
> + asm volatile("fdc %%r0(%0)" : : "r" (&pdir_ptr[7]));
NACK - keep it simple with the original proposed patch.
> PS: in this doc feb96a6.pdf (easy to find) it was said:
> "[snip]
> Entries in the PA 7200 and PA 8000 caches are stored in lines
> of 32 bytes.
> [snip]
>
> Because one-word writes occur in the I/O system, for registers,
> semaphores, or short DMA writes it was necessary that the I/O
> adapter implement a one-line-deep cache to buffer cache lines,
> so that these one-word writes could be executed by performing
> a coherent read private transaction on the Runway bus, obtaining
> the most recent copy of the cache line, modifying it locally in
> cache, and finally writing the modified line back to main memory.
...
> 2 thinks:
> - it seems to confirm that cache line is well 32bytes wide ;-)
>
> - for 'one word writes...' how should it be implemented?
"one word writes" refers to DMA writes, not CPU writes.
> It look like the sba_iommu driver:
> "READ_REG(ioc-ioc_ha_IOC_PCOM); /* flush purges */
> but without more detailed docs on U2/UTurn ccio, I don't know how to
> implement matter, sorry.
The IOMMU driver programs the IO Pdir with the results of "lci" instruction
and this should be all the IOMMU needs to coherently read/modify/write
the cacheline that the "one word" DMA write is targeting. In short,
it's already implemented or I'd think we'd see much worse problems
on ccio platforms.
hth,
grant
>
>
>
> ---
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