On Tue, Aug 20, 2013 at 06:55:48PM +0530, Sourav Poddar wrote:
> The patch add basic support for the quad spi controller.
>
> QSPI is a kind of spi module that allows single,
> dual and quad read access to external spi devices. The module
> has a memory mapped interface which provide direct interface
> for accessing data form external spi devices.
Applied, but please use subject lines appropraite for the subsystem and
one other thing...
> +static irqreturn_t ti_qspi_threaded_isr(int this_irq, void *dev_id)
> +{
> + struct ti_qspi *qspi = dev_id;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&qspi->lock, flags);
> +
> + if (qspi->stat & WC)
> + complete(&qspi->transfer_complete);
> +
> + spin_unlock_irqrestore(&qspi->lock, flags);
> +
> + ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
This is doing a NAPI style thing where it suppresses interrupts while
the interrupt completes however the transfer functions expect an
interrupt per word.
Then again there's no FIFO in the hardware so we'd overflow or underflow
anyway - is there any way of detecting the underflow or overflow other
than a timeout later on (which the driver will do)?
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