On 07/06/13 21:39, Felipe Balbi wrote: > sounds like there's something left in FIFO which is not getting read > out, then we end up timing out. > > Can you try the patch below ? It's patch of a bigger patchset which I > still need to clean a few things up, but they should be very close to > being ready. IIRC, one of the patches creates a problem for N900 (only) > which gets fixed later, I just need to combine those two patches into > one to avoid the regression. > > diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c > index aa3b91e..471b434 100644 > --- a/drivers/i2c/busses/i2c-omap.c > +++ b/drivers/i2c/busses/i2c-omap.c > @@ -1022,9 +1022,8 @@ omap_i2c_isr_thread(int this_irq, void *dev_id) > } > } while (stat); > > - omap_i2c_complete_cmd(dev, err); > - > out: > + omap_i2c_complete_cmd(dev, err); > spin_unlock_irqrestore(&dev->lock, flags); > > return IRQ_HANDLED; > With this change the boot becomes unreliable: [ 3.024322] V2V1: 2100 mV [ 4.049530] omap_i2c 48070000.i2c: timeout waiting for bus ready [ 5.059417] omap_i2c 48070000.i2c: timeout waiting for bus ready [ 5.059448] twl: Write failed (mod 9, reg 0xe5 count 1) and this continues. I did manage to boot once, and running i2cdump printed each byte very slowly, and with 0xff as the data. Tomi
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